SpaceRegisters

From Linux PARISC Wiki
(Difference between revisions)
Jump to: navigation, search
(PA-RISC Registers)
m (formatting update)
Line 9: Line 9:
 
== Instructions ==
 
== Instructions ==
 
There are two types of instruction which reference memory; those with
 
There are two types of instruction which reference memory; those with
2-bit '`s`' fields and those with 3-bit '`s`' fields.
+
2-bit '<tt>s</tt>' fields and those with 3-bit '<tt>s</tt>' fields.
  
Instructions with a 3-bit `s` field are straightforward.  The value of
+
Instructions with a 3-bit <tt>s</tt> field are straightforward.  The value of
the `s` field directly specifies which of the 8 space registers to use.
+
the <tt>s</tt> field directly specifies which of the 8 space registers to use.
  
Instructions with a 2-bit `s` field have two cases.  If `s` is 1-3, we use
+
Instructions with a 2-bit <tt>s</tt> field have two cases.  If <tt>s</tt> is 1-3, we use
the corresponding space register (`sr1-sr3`).  If the value in the `s` field
+
the corresponding space register (<tt>sr1-sr3</tt>).  If the value in the <tt>s</tt> field
is 0, we do not use space register 0.  Instead, we use one of `sr4-7` as
+
is 0, we do not use space register 0.  Instead, we use one of <tt>sr4-7</tt> as
 
determined by the top two bits of the '''base register'''.
 
determined by the top two bits of the '''base register'''.
  
 
== In Linux ==
 
== In Linux ==
In Linux, `sr4-7` are always set to the same value.  When in kernel space,
+
In Linux, <tt>sr4-7</tt> are always set to the same value.  When in kernel space,
 
they are 0.  In user space, they have the value for the task we're
 
they are 0.  In user space, they have the value for the task we're
 
currently executing.
 
currently executing.
  
What we were trying to do in `pacache.S` was use an instruction (flush
+
What we were trying to do in <tt>pacache.S</tt> was use an instruction (flush
 
instruction cache) as if it were a 2-bit-s instruction when it's actually
 
instruction cache) as if it were a 2-bit-s instruction when it's actually
a 3-bit-s instruction.  This led to the processor using `sr0` instead of
+
a 3-bit-s instruction.  This led to the processor using <tt>sr0</tt> instead of
one of `sr4-7`.  The assembler now errors on this case, causing us to find
+
one of <tt>sr4-7</tt>.  The assembler now errors on this case, causing us to find
 
a bug.
 
a bug.
  
 
Just to make things harder, there is a 2-bit-s version of flush
 
Just to make things harder, there is a 2-bit-s version of flush
 
instruction cache, but it's only available on pa2.0 processors, so we
 
instruction cache, but it's only available on pa2.0 processors, so we
don't want to use it.  Instead we use `sr4` (since `sr4-7` all have the same
+
don't want to use it.  Instead we use <tt>sr4</tt> (since <tt>sr4-7</tt> all have the same
 
value in Linux).
 
value in Linux).

Revision as of 10:25, 31 May 2014

Contents

PA-RISC Processor Registers

Register usage for Linux/PA-RISC is documented in the Linux kernel source tree in the file Documentation/parisc/registers: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/parisc/registers

PA-RISC Space Registers and How to use them

Instructions

There are two types of instruction which reference memory; those with 2-bit 's' fields and those with 3-bit 's' fields.

Instructions with a 3-bit s field are straightforward. The value of the s field directly specifies which of the 8 space registers to use.

Instructions with a 2-bit s field have two cases. If s is 1-3, we use the corresponding space register (sr1-sr3). If the value in the s field is 0, we do not use space register 0. Instead, we use one of sr4-7 as determined by the top two bits of the base register.

In Linux

In Linux, sr4-7 are always set to the same value. When in kernel space, they are 0. In user space, they have the value for the task we're currently executing.

What we were trying to do in pacache.S was use an instruction (flush instruction cache) as if it were a 2-bit-s instruction when it's actually a 3-bit-s instruction. This led to the processor using sr0 instead of one of sr4-7. The assembler now errors on this case, causing us to find a bug.

Just to make things harder, there is a 2-bit-s version of flush instruction cache, but it's only available on pa2.0 processors, so we don't want to use it. Instead we use sr4 (since sr4-7 all have the same value in Linux).

Personal tools