From Linux PARISC Wiki
< User:Alex Ivanov(Difference between revisions)
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| − | = TO-DO =
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| − | Ideas to check:
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| − | <pre>
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| − | The drivers/video/aty uses
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| − | an endian config bit DRM doesn't use, but I haven't tested whether
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| − | this makes a difference and how it is connected to the overall picture.
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| − | </pre>
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| − | <pre>
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| − | The Rage128 product revealed a weakness in some motherboard chipsets in that there is no mechanism to guarantee
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| − | that data written by the CPU to memory is actually in a readable state before the Graphics Controller receives an
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| − | update to its copy of the Write Pointer. In an effort to alleviate this problem, we‟ve introduced a mechanism into the
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| − | Graphics Controller that will delay the actual write to the Write Pointer for some programmable amount of time, in
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| − | order to give the chipset time to flush its internal write buffers to memory.
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| − | There are two register fields that control this mechanism: PRE_WRITE_TIMER and PRE_WRITE_LIMIT.
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| − | In the radeon DRM codebase I didn't found anyone using/setting those registers. Maybe PA-RISC has some problem here?...
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| − | </pre>
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Latest revision as of 08:11, 14 February 2015
