User:Alex Ivanov/DRM

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Revision as of 15:39, 6 September 2013 by Alex Ivanov (Talk | contribs)

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Ideas to check:

The drivers/video/aty uses
an endian config bit DRM doesn't use, but I haven't tested whether
this makes a difference and how it is connected to the overall picture.
The Rage128 product revealed a weakness in some motherboard chipsets in that there is no mechanism to guarantee
that data written by the CPU to memory is actually in a readable state before the Graphics Controller receives an
update to its copy of the Write Pointer. In an effort to alleviate this problem, we‟ve introduced a mechanism into the
Graphics Controller that will delay the actual write to the Write Pointer for some programmable amount of time, in
order to give the chipset time to flush its internal write buffers to memory.
There are two register fields that control this mechanism: PRE_WRITE_TIMER and PRE_WRITE_LIMIT.

In the radeon DRM codebase I didn't found anyone using/setting those registers. Maybe PA-RISC has some problem here?...
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