User:Alex Ivanov/DRM

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Ideas to check:

The Rage128 product revealed a weakness in some motherboard chipsets in that there is no mechanism to guarantee
that data written by the CPU to memory is actually in a readable state before the Graphics Controller receives an
update to its copy of the Write Pointer. In an effort to alleviate this problem, we‟ve introduced a mechanism into the
Graphics Controller that will delay the actual write to the Write Pointer for some programmable amount of time, in
order to give the chipset time to flush its internal write buffers to memory.
There are two register fields that control this mechanism: PRE_WRITE_TIMER and PRE_WRITE_LIMIT.

In the radeon DRM codebase I didn't found anyone using/setting those registers. Maybe PA-RISC has some problem here?...

Regarding "colors in 24bpp mode are wrong":

Are the colours still wrong with current xf86-video-ati? There have been
some fixes related to that recently.

Still actual when using xorg of 1.12.4 version on stable 3.11.1 kernel. Maybe build X and related packages from VCS?

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